1. Field of the Invention
This invention relates generally to the fabrication of memory arrays. In particular, the invention relates to a method of forming a highly planar surface through whose use the process of integrating CMOS metal layers and memory junction layers will be improved.
2. Description of the Related Art
For most non-volatile memory fabrication processes, one of the main challenges is to connect the memory junction layer (the layer containing the memory devices) to a CMOS metal layer below it. The critical junction layer of non-volatile memory is normally placed above many metal layers. Depending upon the particular circuit design, there is at least one and perhaps as many as five layers of metal below the memory junction layer. New memory types, such as field induced MRAM (external magnetic fields used to change device magnetizations) and spin torque transfer memory (device magnetizations changed by the torque of conduction electrons) require the critical junction layer to be processed at the back-end of the line due to the anneal temperature limitation. For all known films (layer depositions) thus far the signal budget is very tight for any production-worthy processes. The requirement for CD budget for the junction layer is very tight across a device array (<2.0% 1 s). To achieve this kind of CD control, it will require a super-flat under-layer surface for the junction layer to be built upon.
As more and more back-end metal layers are built on a wafer, the global and local wafer flatness and warpage deteriorate significantly due to the built-in stress and process variations. In addition, the back end of line processes normally consist of Cu CMP (chemical mechanical polishing) processes. In each metal layout, there are normally many Cu lines and vias on the same layer. This kind of layout is normally difficult for the CMP process to planarize across the wafer surface. The following figures will schematically illustrate the prior art methodology for integration of a CMOS metal layer with an MTJ memory cell (or other similar circuitry that includes integrated active devices) formed above it.
Referring to FIG. 1a, there is shown schematically an overhead view of an exemplary layout (100) of metal (conducting) lines (10), and metal studs (20), surrounded by dielectric layers (210), that would typically be presented as the uppermost surface of a lower CMOS integrated circuit level. The studs provide the prepared sites for making the required interconnections between the CMOS circuit level and individual memory cell devices to be formed in a device level above the CMOS level. In the discussions that follow, these studs may also be denoted as “connection pads”, which denote the same type of structures at which connections between CMOS circuitry and active devices are to be made. It is the task of circuit integration to fabricate the additional levels of active device circuitry on this CMOS level layout so that the additional levels of active circuitry are properly integrated with the CMOS circuitry through contact to the CMOS studs and connection pads.
FIG. 1b is a schematic view of a cross-sectional cut through the circuit of FIG. 1a through the horizontal line labeled 1b. The cut provides a cross-sectional view of the two lines (10), two of the studs (20) and the dielectric material (210) surrounding them. It is understood that there may be many more CMOS levels beneath this level, but for the purposes of describing the invention herein, it is only necessary to deal with that portion of the CMOS level that is in immediate contact with the device level formed above it.
Referring now to FIG. 2a, there is shown an overhead schematic view of a more realistic prior art layout of CMOS lines and studs (shown below in FIG. 2b) on which has been indicated an array of twelve exemplary “objects,” presented as four columns of three objects in a column. This circuit is similar to that in FIG. 1a, but it has these additional objects that include the active devices and non-active elements that are used to improve the structural qualities of the circuit. In addition, this circuit includes the deposition and patterning of buffer layers (60) of conducting material that are formed over the Cu material ((10), and (20) in FIG. 2b) of the CMOS level. The buffer layers are for the purpose of preventing diffusion of Cu into the device level and to present a smooth surface on which to form the devices. All devices will be formed on these buffer layers.
In order to discuss the structure of these exemplary objects and the roles they play, they are labeled A through L. Objects A, B, G, H and I, that are shown as ellipses with large X's drawn within them, are actually not physical objects, but are regions where devices could be placed to improve the integrity of the circuit, but are not so placed. Objects (A and B) and (G, H and I) are positioned, respectively, on rectangular buffer layers (60) formed contiguously over Cu wiring (10) and (11) in the CMOS level that are shown in FIG. 2b. (C, D, E, F) and (J, K and L) are positioned over (shaded) dielectric regions (210) in the CMOS level. There is no large buffer layer formed contiguously over these dielectric regions, rather small individual circular buffer layers (60), shown as annular regions, are formed beneath junction devices of smaller radii.
E, F, J and K, in this exemplary circuit, label real studs that connect to the CMOS level. They are covered with circular patterned buffer layers (60) shown as small annular regions extending beyond the circular peripheries of junction devices (50) that are formed on these buffer layers. Junction devices formed on the real studs E, F, J and K are “active” junctions because they are electrically connected to the studs in the CMOS level. C, D and L are real junctions that are formed on circular buffer layers, but, in this exemplary circuit, there are no studs beneath them. These junctions are, therefore, called “dummy” junctions, because they have no electrical activity. They are formed to provide structural stability to the circuit. Dummy junctions are drawn with dashed circular peripheries to indicate their lack of activity. For performance purposes, we are supposing that active devices are not needed at locations A, B, G, H and I. For structural purposes, however, it would be desirable to form them there. Unfortunately, if they were formed there, they would be rendered active by contact with the Cu wiring beneath them, so they are “not allowed,” and are not formed.
A “dummy” stud is a region in the CMOS level over which a memory junction is formed but under which there is no actual stud. Thus, the memory junction is fully formed, but does not act because it is electrically isolated from elements in the CMOS level. The non-existent dummy stud is shown as an annular region (30) drawn with a dashed line around a memory junction (70), also drawn with a dashed outline to indicate its inactivity.
Each stud, active and dummy, has a memory junction (or other like device) formed upon it. The memory junction is not formed directly on the stud, but is formed on a buffer layer that is deposited on the stud to control diffusion from the Cu forming the stud into the devices formed on the stud. These buffer layers are deposited and patterned and the devices are formed on them. The buffer layer formation will be discussed more fully below.
The memory junction is formed in the upper device layer that is integrated with the lower CMOS layer. The active studs have active junctions (50), formed on them. The dummy studs have dummy (inactive) junctions (70) formed on them. In addition, there are regions where dummy studs (75) should exist, but are not allowed (drawn with large elliptically surrounded X's). Dummy studs (A, B, G, H, I) and inactive devices on them are not allowed in regions where there is already a Cu line beneath a buffer layer, as lines (10) and (11). As previously mentioned, the fabrication of the studs includes the formation of a buffer conduction layer (60) that both prevents Cu diffusion into the surrounding materials and facilitates the smooth deposition of the memory junction layers to be formed in the upper device level. This second role of the buffer layer is required because the upper surface of the Cu conduction line deposition is typically too rough for effective formation of a memory device directly upon it. The nature of this fabrication is such that buffer layers may be formed in different sizes, such as the large rectangular layer beneath A, B, G, H and I and the smaller circular layers beneath E and K. It is difficult to smoothly pattern buffer layers in different sizes and designs and, in addition, large regions of buffer layer are prone to peeling during annealing.
Referring now to schematic FIG. 2b, there is shown a cross-sectional cut through the dashed line labeled 2b in FIG. 2a, showing two of the active memory junctions (50) formed on the buffered conduction layer (60) and contacting the active studs (20).
Several issues arise in the context of this type of fabrication as was already mentioned above. First, there is very little flexibility in the formation of a junction layer dummy pattern layout. Second, it is very difficult to form a flat and smooth buffer layer on the same fabrication surface when different pattern sizes are required. Third, a large buffer layer pattern is prone to peeling during annealing of the device structures. It would be advantageous to produce a fabrication in which the patterned layers of buffer material were both small and uniform.
Referring next to FIG. 3a, there is shown a schematic overhead view of another prior art fabrication and, in FIG. 3b, there is shown a schematic side view of a vertical cut through the line labeled 3b of the fabrication in FIG. 3a. The overhead view in 3a shows the buffer layers (60) and active (50) and dummy (70) devices. Note that the dummy devices are drawn with broken line peripheries to more clearly indicate that they are not connected to any electrical portions of the CMOS layer.
An observation of the side view in FIG. 3b shows that in this fabrication, a device layer level with additional structure (200) has been formed over the CMOS level (100). The device level, which may be called a via connection layer (VAC layer), includes dielectric material depositions (215) formed over an etch-stop layer (95) that caps the CMOS level. There can be seen both active devices (50), and inactive dummy devices (70). The active devices are formed on a buffer layer (60) and are connected to the CMOS level through vias (80), formed as part of this via connection layer. The dummy devices are left unconnected to the lower CMOS level and are now separated from the lower level by the thickness of the dielectric layer (215). Thus, because they would not directly contact a Cu layer in the CMOS level, these dummy devices are allowed, unlike the dummy devices in FIG. 2a that were not allowed (A, B, G, H and I in FIG. 2a).
The fabrication of FIG. 3a also has integration difficulties associated with it, particularly a difficulty in fabricating a flat, smooth VAC layer without properly filled dummy patterns and a difficulty in patterning a flat/smooth buffer layer due to the VAC underlayer.
Issues involving surface planarity have been discussed in the prior art. Inoh et al. (U.S. Pat. No. 7,009,273) discloses a dummy pattern formed at the ends of a DRAM array so that photolithograpy or etching processes will not vary.
Zhong et al., (US Patent Application 2008/0225576) discloses dummy MTJ devices to eliminate delamination during CMP. This patent application is assigned to the same assignees as the present invention.
Coleman (U.S. Pat. No. 5,850,366) teaches the formation of a memory array using dummy cells to provide a reference voltage.
None of this prior art addresses the problem of surface planarity in the manner of the present invention.